Micrel, Inc.
MIC2310
July 2008
27
M9999-070108-A
Shorted C
PRIMARY
Detector Asserts HW_FLT After
Primary OC Event
The diagram in Figure 14 illustrates the behavior of
the controller to a shorted C
PRIMARY
capacitor condition
after steady-state operation is achieved via a nominal
start-up and after a primary OC event has occurred.
As described previously, during a primary OC event,
the C
PRIMARY
capacitor is discharged as part of setting
the primary OC detector response time, t
POC
. In order
to prevent a false C
PRIMARY
short detection from
occurring while the CPRIMARY pin is being
intentionally discharged, the C
PRIMARY
short detection
circuit is disabled when the primary OC detector
detects an overcurrent. In addition, the C
PRIMARY
short
detection circuit is not re-enabled until after a time
delay, t
SCPDETPOR
, once the primary OC detector no
longer detects an overcurrent. This delay time should
allow a capacitor of reasonable size to be charged
back up above V
PRIH
, even if it has been discharged to
0V, such that a false C
PRIMARY
short is not indicated
when the C
PRIMARY
short detection circuitry is re-
enabled.
In the timing diagram, C
PRIMARY
becomes shorted
during the primary OC event. When the CPRIMARY
pin voltage falls below V
PRIL
, the t
POCSENSE
timer is
enabled. Once this timer times out, the circuit breaker
is tripped, I_FLT is asserted, the GATE drive circuitry
is disabled, the GATE fault-mode pull-down current
sink is enabled, and the DISCH output goes high. As
the external MOSFET is turned OFF, the output
current drops and an overcurrent condition is no
longer detected. This initiates the t
SCPDETPOR
timer.
Since C
PRIMARY
does not charge back up above V
PRIH
before this timer expires, HW_FLT is asserted after
the t
SCPDETPOR
time. To repair the damaged C
PRIMARY
capacitor and reset the HW_FLT digital output, the
service processor instructs the main supply to turn off
the V
CC
supply voltage to the controller such that V
REG
falls below the controllers V
VREG(UVLOL)
threshold
voltage.
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